Verilog, Sata, Python, Perl, Usb, PCI Express, constrained random verification, Uvm, functional coverage, VMM, systemverilog, DV methodologies

cache coherency , Verilog, DDR Subsystem, SoC Verification, Uvm, Assertion coverage closure, CHI-based interconnect verification, Functional Code Toggle, systemverilog, CPU PCIE Security