As a Design Verification Engineer at IBM, you will be responsible for verifying SoC logic blocks and ensuring robust chip initialization and reset sequences. You will develop test benches, apply verification methodologies, debug RTL designs, and collaborate with the design team to ensure successful delivery of functional and high-quality hardware.

Key Responsibilities:

Design & Specification Analysis: Understand design specifications, PowerOn specifications, boot firmware, and reset flow.
Verification Environment Development: Develop test benches and verification environments using IBM BIST verification tools and methodologies.
Debugging & Troubleshooting: Debug fails using waveform and trace tools, debug RTL code, and work with design teams to resolve logic design issues.
Test Scenario Development: Write complex test scenarios, drive verification coverage, and ensure closure.
Collaboration: Work effectively with global teams, providing updates, reporting issues, and ensuring delivery timelines are met.
Coverage & Analysis: Conduct functional and code coverage analysis, identify gaps, and implement corrective actions.

Required Education:

Bachelor's Degree

Preferred Education:

Bachelor's Degree

Required Technical and Professional Expertise:

4+ years of experience in design verification with demonstrated execution on SoC logic blocks
Strong knowledge of SoC verification, chip reset sequences, and initialization (for SoA)
Proficiency in HDLs such as Verilog and VHDL
Programming skills in C, C++, Python, or Perl
Experience developing testbench environments and writing complex test scenarios
Hardware debug skills with relevant project experience

Preferred Technical and Professional Experience:

Knowledge of chip initialization, SCAN, and BIST
Scripting expertise with applied project experience
Experience writing verification test plans and performing functional/code coverage analysis

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