Rtl Design, ASIC development cycle, ASIC design methodologies, Accelerator Systems, architecture, Verification

C, Usb, Pcie, Verilog, Networking Protocols, Ethernet, Python, Palladium, systemverilog, hybrid flows, emulation methodologies, Zebu, Protium

Perl, Verilog, Python, Tcl, Cadence Palladium, Siemens Veloce, Synopsys ZeBu, systemverilog

power analysis, Verilog/SystemVerilog, ASIC Design, RTL Coding