low power design, systemverilog, Rtl Design, Architecture, ASIC ASIC design

C, Usb, Pcie, Verilog, Networking Protocols, Ethernet, Python, Palladium, systemverilog, hybrid flows, emulation methodologies, Zebu, Protium

Perl, Verilog, Python, Tcl, Cadence Palladium, Siemens Veloce, Synopsys ZeBu, systemverilog

Verilog, Design Verification, implement IP/SoC verification plans, systemverilog, C/C++, ASIC development cycles