Host & Userspace, Rtl Design, Synthesis, ASIC development cycle, ASIC design methodologies, Verification, Infra Silicon Enablement

Tcl, Mercurial, Svn, DDR, Git, Pcie, Perl, Ethernet, Arm, Python, RISC-V, systemverilog, AMBA, Emulation, Design Verification infrastructure, System Verilog Assertions

power analysis, Verilog/SystemVerilog, ASIC Design, RTL Coding