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Showing 8 jobs
Skills:
C, Perl, Verilog, Gdb, Python, Indago, SOC design, Cadence
Skills:
physical design constraints, memory interconnect architecture, ASIC Design, Digital Design, low-power design techniques, architectural simulators, power estimation frameworks
Skills:
Soc Architecture, systemverilog, CAD Tools, Rtl Design, SoC Integration, Asic
Skills:
Perl, Verilog, Gdb, Python, Indago, SOC design, Cadence
Skills:
Soc Architecture, AMBA AXI CHI protocols, HW SW co-design, Memory subsystem architecture, PCIe CXL UCIe, Silicon bring-up and debugging, RTL and microarchitecture understanding, Performance analysis and simulation
Skills:
Tcl, Python, Perl, systemverilog, System Verilog Assertions, Emulation
Skills:
Embedded Software, Rtl Design, Technical Specifications, IP selection strategies, Verification
Skills:
Perl, Verilog, Python, Tcl, Cadence Palladium, Siemens Veloce, Synopsys ZeBu, systemverilog
