Fcoe, spyglass, Verilog RTL coding, Synopsys Design Compiler, ASIC debugging, Multi-domain clock synchronization, High performance memory subsystems, High-speed serial interfaces, LEC, Networking protocols Ethernet, Verplex

Shell scripting, Static Timing Analysis, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, Git, Dft, Synthesis, AXI-based interconnects, LINT, cdc, Sta, CXL, RDC

C, Vcs, Perl, Verilog, spyglass, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, EVE, Veloce, ASIC Design, formal verification

Digital RTL Design, VHDL, Timing Analysis, Logic Synthesis, Low-Power Design Techniques, systemverilog

multi-domain clock synchronization, spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, high performance memory subsystems, ASIC debugging

Verilog, Python, Perl, Vcs, Gdb, bring-up lab debug, Debussy, ASIC design flow, floor-planning, Timing Analysis, Eco, Rtl Design

Synthesis, RTL code in Verilog, SoC integration, Timing Closure, RTL logic design, micro-architecture specifications, Verification, timing optimization, assertions coverage analysis

Pcie, Version Control, Ethernet, RTL synthesis, Documentation, Timing Closure, verification processes, silicon bring-up, bare metal firmware development, SERDES, AI tools like Cursor