Silicon Validation, Shell, Perl, automation, Python, Scripting, power analysis, Emulation, Simulation, performance models, power models, power estimation tools, NSP architectures

reactor , Station service transformer, Capacitor bank, HV MV cable ampacity and heat dissipation sizing calculation, Overall Substation Equipment Layout Plan, Power Transformer, Insulation Coordination calculation, Power System Analysis, Substation primary engineering, MV switchgear, Cable Raceway Layout Plan, HV GIS switchgear

Rtl Design, Synthesis, ASIC development cycle, ASIC design methodologies, architecture, Verification, Power

Tcl, Mercurial, Svn, DDR, Git, Pcie, Perl, Ethernet, Arm, Python, RISC-V, systemverilog, AMBA, Emulation, Design Verification infrastructure, System Verilog Assertions

Debuggers, power-saving mechanisms, trend detection, Data Analysis, tester-to-system correlation, DMM, DAQ, Oscilloscopes, power characterization, metric extraction, AI-enabled workflows

User Support, power analysis, Verilog/SystemVerilog, ASIC Design, RTL Coding, Infra