Perl, Python, Machine Learning, Deep Learning, Cadence SKILL language, PCELL development, LLM techniques

cadence schematic capture , Verification tools - CALIBRE, Cadence Tools, Memory layout design, AI automation in layout, ElectroMigration, Hercules, SKILL Programming, Physical verification LVS, ERC, DRC, Script Programming, Antenna, Chip Integration, Floor-planning, Hierarchy layout

Process design rules, Analog layout design, Design verification tools, Layout methodologies, Voltage drop, Micro-floor planning, Ir, Floorplans, Signal planning, Esd, TSMC N3 technology, Electron migration, High speed SerDes layouts, Power grid

CMOS, Cadence, signal shielding, Analog Layout

Routing, DC-DC Converter, Layout optimization, High Voltage BCD Power Management technologies, Analog Mixed-Signal Layout, LVS, ERC extraction, Latch-up prevention, Calibre, Isolation structures, DRC, Floor Planning, LDO, Cadence Virtuoso, Guard rings, PMIC, Device placement

hierarchical layout techniques, 3nm technology, Mentor Graphics Calibre, custom layout design, Totem tools, Cadence Innovus, device matching, Cadence XL, designing custom analog blocks, full-chip integration, IR drop analysis, low-parasitic layout practices