Search Jobs
Search by job, company or skills
Search by job, company or skills
Showing 6 jobs
Skills:
System Verilog, Gate Level Simulations, Building test benches from scratch, ASIC verification using UVM
Skills:
System Verilog, Building test benches from scratch, ASIC verification using UVM, Gate Level Simulations
Skills:
System Verilog, Building test benches from scratch, ASIC verification using UVM, Gate Level Simulations
Skills:
Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification
Skills:
Verilog, Design Verification, implement IP/SoC verification plans, systemverilog, C/C++, ASIC development cycles
Skills:
Design Verification, ASIC Design, Verification Planning, systemverilog, Rtl Design
