Uart, Spi, Arinc, Pcie, Python, Tcl, Cadence-Xcelium, DO-254, Siemens Questasim, VHDL, Rivera-PRO, AXI4, Synopsys-VCS

JIRA, Jenkins, Analyzing verification issues, Intel Quartus, Xilinx Vivado, FPGA design and verification following the DO-254 process, Interpreting schematics and layout diagrams, RTL design using VHDL, Electronic components and circuit design flow, Microchip Libero SoC