Scripting, Pcie, Ethernet, cdc, Security Protocols, Design qualifications, Verilog RTL design, Silicon IP development process, Linting, Simulation, Networking IP solutions

manufacturing drawings , 3D Modeling, Sheet metal and weldments, ANSI standards, Autocad, AWS specifications

manufacturing processes , material properties , PLM platform like Enovia, surface coating, tolerance stack-up analysis, Heat Treatment, product structure, 2D drawings, Catia V5

altium , Usb, Spi, Jira, Plm, I2c, Gbit Ethernet, Dfm, Simulation Tools, Dft, dtc, Hardware development life cycle, Embedded projects, Autocad, Hardware design and testing

manufacturing drawings , Solidworks, Clamps, Routing Practices, Clips, Autocad, BOMs, connectors, Terminals, Coverings, System Diagrams, Electrical Schematics, Wire Harness Design, Splices

Mentor Graphic Calibre DRC, Cadence VLE, TSMC 3nm, Design and development of critical analog mixed-signal custom digital block, LVS, Full chip level integration support

RDC, Pipelining techniques, Datapath architecture, cdc, SpyGlass Lint, RTL coding expertise in Verilog, Clock and Reset domain crossings, micro-architecture development, ASIC SoC design flow, systemverilog, FSM design

manufacturing processes , Automation, Robotics, Power Transmission, Development of Machines, Vendor Management