Unix, Lsf, Jenkins, Git, Shell, Linux, Verilog, Gitlab, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, UGE, LINT, Low Power, Slurm

test equipment , Usb, Spi, Gpio, Pcie, Perl, Verilog, Debugging, Ethernet, I2c, Python, Tcl, HW testing, traffic analysers, DDR SDRAM, Memory architectures, Rtl Design, VHDL, Xilinx technology and tools, test generators, DMA technologies

Uart, Spi, Verilog, I2c, LINT, cdc, MAS development, Sub-system design, SoC integration, ip design, Quality check flows, AMBA bus protocols, Axi, APB, RTL Coding, Medium complexity protocol, AHB, Microarchitecture

Pcie, timing-aware micro-architecture, UCIe, high-speed lane alignment, SystemVerilog RTL, CXL, physical-closure collaboration, deskew, design-for-test

Verilog, multi-clock designs, Synthesis, formal verification, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Timing Concepts, asynchronous interfaces, System-Verilog

Ecos, FCR ECR reviews, RTL construction, SoC DV test plans, PPA targets, Clock Reset UPF, constraint and timing convergence, IP integration

Ecos, Clock Reset UPF, IP integration, FCR ECR reviews, timing convergence, RTL construction, SOC design

Soc Architecture, Physical design interaction, SoC integration, Formal verification techniques and tools, Verilog RTL development, UPF and low-power methodologies

Soc Architecture, Physical design interaction, SoC integration, Formal verification techniques and tools, Verilog RTL development, UPF and low-power methodologies