Assembly Language, Unix Shell, Verilog, Tcl, Python, Perl, Uvm, SVA, systemverilog, C Language

Unix Shell, Tcl, Python, Perl, Synthesis, ASIC Design Flow, Innovus, Timing Analysis, Cadence EDA tools, Tempus, formal verification, Voltus, Genus, Physical Designing, power analysis

Python, Analog Mixed-Signal Design, Stability Compensation, Precision Circuits, Advanced CMOS Processes, Noise PSRR, Cadence Virtuoso, PVT Mismatch Corners, Variation Reliability, Monte Carlo Aging, Spectre