FPGA Design, Static Timing Analysis, Optimization, Synthesis, Timing Closure, Digital ASIC FPGA architectural design, systemverilog, Code coverage analysis, RTL design using Verilog

synplify , C, Pcie, Verilog, Python, System Verilog, Usb, Multimedia, Perl, Ethernet, Tcl, hardware schematics, Xilinx FPGA based design implementation, ARM CPU, FPGA design tools, FPGA RTL coding, VHDL, DDR emulation, Verification, Lab tools, Synthesis, UFS, FPGA constraint setup, Xilinx Ise, Vivado, Timing Closure, csh, DDR5, Audio, WIFI