Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC

System Verilog, Environment Development, Uvm, Design Verification, Functional Verification, Test Plan Generation

monitors, coverage analysis, Uvm, scoreboards, checkers, formal verification, systemverilog, constraint random testing

power optimization , Verilog, static timing analysis, Uvm, Synopsys, SV-based testbenches, Timing Analysis, Mentor Graphics, digital design flow, EDA Tools, coverage-driven verification, systemverilog, Rtl Design, Cadence, VHDL, Simulation

C Programming Language, Tcl Scripting, Embedded programming languages, Waveform viewers, Low level APIs on Microcontrollers, Simulators, Verification EDA Tools, Bare-metal programming