Pvs, Makefile, Tcl, Python, Perl, hierarchical physical design strategies, EM-IR, ASIC design flow, Physical Verification, deep sub-micron technology issues, Physical Design, Innovus, Quantus, Tempus, Voltus, formal verification, Timing Closure, Tk, Cadence implementation tools, Genus

Unix Shell, Verilog, Perl, Assembly Language, C Language, MISRA coding guidelines, EDA simulation, ISO 26262, systemverilog, fault simulation tools

Spi, Pcie, Usb, Dac, Uart, Ethernet, ADC, power-aware simulations, gate-level simulations, PLLs, Mentor Graphics Questa, Cadence Xcelium, low-power verification using UPF, Uvm, security IPs, I²C, functional coverage, eSPI, constrained-random verification methodologies, systemverilog, SoC-level verification, crypto engines, Synopsys VCS, Flash Memory, Analog IPs, ARM-based microcontrollers

Python, Analog Mixed-Signal Design, Stability Compensation, Precision Circuits, Advanced CMOS Processes, Noise PSRR, Cadence Virtuoso, PVT Mismatch Corners, Variation Reliability, Monte Carlo Aging, Spectre