Sr Principal Design Engineer

Key Responsibilities

• Own complete DFT execution across projects, including planning and implementation
• Define test architecture and evaluate DFT requirements for complex SoC designs
• Implement RTL changes to support scan insertion and testability requirements
• Perform scan insertion, LEC (Logic Equivalence Checking), and low-power CLP analysis
• Develop and manage timing constraints for test-mode timing closure
• Execute ATPG for multiple fault models and analyze results for coverage improvement
• Implement and verify boundary scan, ACJTAG, and IEEE 1500 standards
• Develop IEEE 1687 (iJTAG) compliant ICL/PDL for manufacturing test flows
• Run zero-delay and timing simulations and debug DFT-related issues
• Support post-silicon bring-up and debug silicon validation issues
• Collaborate with customers and support marketing/pre-sales technical engagements
• Work on high-speed, low-power semiconductor designs and ensure test quality