Senior Staff DFT Engineer
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(www.enchargeai.com)
Senior Staff DFT Engineer
Location: Greater Bengaluru Area (Hybrid-2 days office,3 days-home) or Remote (any where in India
About Company:
EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge's robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today's best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.
Developing silicon for Edge Computing isn't just about speed; it's about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.
As the Design for Test (DFT) Senior staff, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.
Key Responsibilities
Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, and MBIST.
Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.
Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Logic BIST.
Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact.
Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.
Technical Requirements
Experience: 10-14 years in DFT, with at least 2 years in a leadership or principal role.
Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus).
Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities and boundary scan (IEEE 1149.1/6).
Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).
Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.
Contact
Uday
[Confidential Information]
Mulya Technologies
Mining the Knowledge Community
Job ID: 151273171
Skills:
Logic Design, Perl, Python, Tcl, Sta, MBIST OCC validation flows, Cadence, Mentor, Physical design flows, SpyGlass DFT rules, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, Digital Circuit Design, SSN design and IEEE 1687 IJTAG standards, Synopsys, RTL design synthesis
Skills:
Logic Design, Tcl, Python, Perl, Mentor, MBIST OCC validation flows, Synopsys, Digital Circuit Design, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, SpyGlass DFT rules, Sta, Cadence, Physical design flows, SSN design and IEEE 1687 IJTAG standards, RTL design synthesis
Skills:
Shell, Tcl, Verilog, Python, Perl, VHDL, MBIST, FPGA prototyping, Timing Analysis, ATPG, fault modeling, FPGA-based DFT methodologies, DFT architecture and implementation, board bring-up, LBIST, synthesis-aware DFT implementation
Skills:
Shell, Tcl, Verilog, Python, Perl, LBIST, MBIST, FPGA prototyping, Timing Analysis, ATPG, DFT architecture, VHDL, fault modeling, FPGA-based DFT methodologies, synthesis-aware DFT implementation, board bring-up, DFT implementation, Scan Insertion
