Logic Design, Perl, Python, Tcl, Sta, MBIST OCC validation flows, Cadence, Mentor, Physical design flows, SpyGlass DFT rules, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, Digital Circuit Design, SSN design and IEEE 1687 IJTAG standards, Synopsys, RTL design synthesis

Logic Design, Tcl, Python, Perl, Mentor, MBIST OCC validation flows, Synopsys, Digital Circuit Design, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, SpyGlass DFT rules, Sta, Cadence, Physical design flows, SSN design and IEEE 1687 IJTAG standards, RTL design synthesis

Shell, Tcl, Verilog, Python, Perl, VHDL, MBIST, FPGA prototyping, Timing Analysis, ATPG, fault modeling, FPGA-based DFT methodologies, DFT architecture and implementation, board bring-up, LBIST, synthesis-aware DFT implementation

Shell, Tcl, Verilog, Python, Perl, LBIST, MBIST, FPGA prototyping, Timing Analysis, ATPG, DFT architecture, VHDL, fault modeling, FPGA-based DFT methodologies, synthesis-aware DFT implementation, board bring-up, DFT implementation, Scan Insertion