Senior Physical Design Engineer
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Experience - 7+years
Location - Hyderabad, Bangalore, Pune and Kochi
Notice Period - Immediate to 60 Days
JD Physical Design -
• In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification.
• Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes.
• Should have experience on programming in Tcl/Tk/Perl.
• Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre).
• Well versed with timing constraints, STA and timing closure.
• Inspirational leadership style, good communication skills, and ability to work in a global environmentIn-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification
• Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes.
• Should have experience on programming in Tcl/Tk/Perl · Well versed with timing constraints, STA and timing closure.
• Inspirational leadership style, good communication skills, and ability to work in a global environment.
Job ID: 145164359
Skills:
redhawk , Python, Perl, Tcl, Sta, Multi-voltage domains, primetime, Foundry PDKs, Tempus, Cadence, Cadence Innovus, Power gating, UPF, Voltus, Implementation tool suite, SDC, Signoff tools, EDA Tools, Physical Design, TSMC, Samsung, CPF, Synopsys, Synopsys ICC2, Low-power design techniques, Timing Analysis
Skills:
static timing analysis, industry-standard EDA tools for physical design and verification, Synthesis, RTL-to-GDS workflows, multi-power domain analysis, Place And Route, low-power design techniques, Clock Tree Synthesis
Skills:
Static Timing, Routing, Physical Verification, Synthesis, Power Efficiency, Custom Clocking, Physical Design, Placement, floorplanning, Formal Equivalency, IR-Drop
Skills:
layout verification , Computer Engineering, System Verilog, Tcl, low-power designs, Electrical Engineering, Computer Science, design rules, Vlsi Design
Skills:
clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, Power Mesh, PNR Floor Plan, Timing Signoff
