Pcie, Perl, Verilog, Python, spyglass, VHDL, DDR memory controllers, CXL

debugging complex IP designs, UVM methodology, test plan reviews, testbench development, systemverilog

simvision , Vcs, Xcelium, Questa, waveform analysis, Uvm, formal verification tools, systemverilog, coverage-driven verification, Verisium

Debugging, Regression Testing, Test Planning, Design Verification, IP Verification, systemverilog, Uvm, Testbench Development, Verification Architecture, Simulation, Coverage Closure