Debugging, Test Planning, Simulation, systemverilog, Uvm, IP verification, Testbench development, Verification architecture, Mentoring

code coverage , closure , Ovm, Perl, Tcl Scripting, Verilog, SDF, automation, Specman, SV, assertions development, constraint randomization, RTL, Uvm, GLS, formal verification, eRM methodology, test-bench development, HVL

Fcoe, Ethernet, spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

Verilog, System Verilog, Functional Verification, LPDDR, Uvm, DDR memory protocols, HBM