Physical Design Verification, Analog Circuit Design, Foundry PDKs, Embedded Design, Layout Design for Analog and Mixed-Signal Blocks

Dac, Custom IP Development, LVS, ADC, Mentoring engineers, PHY Power Management, LDO, ERC, DRC, Analog Mixed-Signal Layout Design, Conducting reviews, Antenna and EMIR verification signoff methodologies, Leading layout activities, High-Speed Analog layouts, Pll

rc extraction , Dac, Tcl, Perl, high-speed analog custom layout, Dfm, LVS, Physical Verification, EDA Tools, ADC, Cadence Virtuoso, ERC, DRC, Skill, Pll, SERDES, EMIR analysis