performance verification of ASICs, assertion-based verification, Uvm, formal tools, ASIC standard interfaces, systemverilog, Design Verification, memory system architecture, verification components

System Verilog, Synthesis, microarchitecture specification, Complex Control Logic, Lint closure, Post-Silicon Debug, Timing Constraints, Networking ASICs, Designing Fabric Network On Chip, RTL coding in Verilog, Digital Design

code coverage , Nvme, System Verilog, Ethernet, Pcie, DDR, Uvm, UCIe, simulation and debug tools, AHB, assertions, functional coverage, CXL, APB, Axi

System Verilog, C, Bug Tracking Tool, Git, Models for performance verification, Synopsys, Monitors, Transactors, Performance test plan development, Cadence, RTL simulations

scoreboard , System Verilog, script development, Uvm, verification closure, verification environment, testbench components, interface agents

Github, Jenkins, Pytest, Git, C, Verilog, System Verilog, Python, Git actions