Physical Design Verification, Analog Circuit Design, Foundry PDKs, Embedded Design, Layout Design for Analog and Mixed-Signal Blocks

Dac, Conducting reviews, ADC, Leading layout activities, Antenna and EMIR verification signoff methodologies, High-Speed Analog layouts, LVS, Custom IP Development, Pll, PHY Power Management, Analog Mixed-Signal Layout Design, ERC, DRC, LDO, Mentoring engineers

Vdc, ADC, Charge pump, density, Antenna, noise fixes, Vlsi Design, custom analog layout design, Virtuoso XL, EDA Tools, RV high voltage flows, LDO, scripting skills, layout validation, Circuit Design, DRCs

rc extraction , bandgap references , shielding , matching , Tcl, Perl, Dfm, high-speed analog custom layout, LVS, latch-up strategies, EDA Tools, clock routing, ADC, Esd, Cadence Virtuoso, ERC, DRC, LDOs, Power Planning, Skill, SERDES, Pll, EMIR analysis

Layout Techniques, Analog Layout Design

Dac, Tcl, Perl, Dfm, LVS, deep sub-micron CMOS, EDA Tools, ADC, ERC, Cadence Virtuoso, DRC, Skill, GAA nodes, FinFET, SERDES, Pll, EMIR analysis