Design Verification, innovus, icc

Perl, Verilog, Python, Tcl, Circuit Design, Dc, ICC, Electrical Checks, systemverilog, Innovus, Physical Verification, Physical Design, Synthesis PnR, Genus, Deep Submicron Technology, device physics

System Verilog, Building test benches from scratch, ASIC verification using UVM

Perforce, static timing analysis, Shell, Verilog, Version Control Systems, Scripting Languages, Python, Git, Perl, Tcl, cdc, Simulation, formal verification, EDA Tools, Rtl Design, Synthesis, SoC Architecture Design, LEC, AMBA protocols, systemverilog, Axi, APB, LINT, AHB, SoC Integration

System Verilog, Gate Level Simulations, Design Verification Fundamentals, formal verification, Interconnects, Coherency Concepts, NoCs, Automated Flows, Uvm

verification methodologies, power and signaling solutions, Physical Design, PD EDA flows