Perl, Verilog, Shell Scripting, LINT, cdc, RTL Quality Checks, Micro Architecture Definition, Connectivity, SOC design, VCLP

Shell, Tcl, Perl, DMA, digital design fundamentals, control data path logic, protocol bridges, low-power design flows, systemverilog, power performance and area optimization techniques, lint CDC RDC synthesis STA constraints, RTL design using Verilog, memory-mapped peripherals, micro-architecture definition, Dft, bus fabrics, debugging skills for simulation synthesis and integration issues