C, System Verilog, Python, low power design, Synthesis constraint generation, Digital architecture, Debugging verification test cases, Embedded uC Designs, Synthesis, Dft, power management, Scripting of design automation, Behavioral coding, Digital RTL, Timing Analysis

Verilog, Pcie, Debugging, Rtl Design, systemverilog, Uvm, CXL, PXC, Vlsi, Digital Design, SoC Verification

Semiconductor, Quality Improvement

static timing analysis, EDA tools for synthesis, VHDL, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, low-power design techniques, digital IC ASIC design, RTL quality tools such as Spyglass Lint CDC RDC

regulators , Verilog, Matlab, Spectre, TX, IC design CAD tools, RX, Mixed signal circuits, DACs, Spice, Filters, ADCs, HSIM, Bandgap bias circuits, Pll

regulators , Verilog, Matlab, IC design CAD tools, RF and Analog Design, Mixed signal circuits, TX, Bandgap bias circuits, RX, Spice, ADCs, Silicon Germanium SiGe BiCMOS, Spectre, Pll, DACs, HSIM, Filters, Bipolar Complementary Metal Oxide Semiconductor technology