Custom layout design, High-speed IPs, Floorplan constraints, High-speed Analog Serdes, Data converters, LVS, Scripting and automation, Analog Macros, IP integration, Physical verifications, Pll, Analog layout techniques, power management, DRC, Ageing and Reliability Compliance, Full Spectrum Verifications, Electrical check

Custom layout design, High-speed IPs, Floorplan constraints, High-speed Analog Serdes, Data converters, LVS, Scripting and automation, Analog Macros, IP integration, Pll, Physical verifications, Analog layout techniques, power management, DRC, Ageing and Reliability Compliance, Full Spectrum Verifications, Electrical check

Static Timing Analysis, AMBA based protocols, Synthesis, DDR4, LINT, DDR protocol, Cadence Tools, Design Verification, cdc, AHB, DDR Integration, IC implementation design and verification tools, LPDDR4, APB, Silicon Bring-up Testing, Axi

System Verilog, Synthesis, microarchitecture specification, Complex Control Logic, Lint closure, Post-Silicon Debug, Timing Constraints, Networking ASICs, Designing Fabric Network On Chip, RTL coding in Verilog, Digital Design

static timing analysis, Perl, Python, EDA tools for synthesis, LINT, cdc, digital design principles, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, RTL quality tools such as Spyglass, RDC, VHDL, low-power design techniques

hardware engineering , Digital Logic Design, Embedded Firmware, Scripting Languages, Jtag, Verilog, System Verilog, IEEE1500, Micro-processor debug, Power management verification, Memory dump, MBIST, UPF, C Language, Scan dump, DFT architecture

MATLAB, EMI thermal co-optimization, Analog mixed-signal IC design, Clarity EMX, Voltage Regulators, Magnetics integration, Simulink, 3DIC package integration, IVR DC-DC converters, Spectre, Inductor modeling, Power management PMIC, Control Loops, 2.5D packaging flows, Cadence Virtuoso

high-speed AMS circuits, SerDes design, lab equipment for testing and characterization, high-speed digital design, circuit simulation and analysis, TX RX and PLL components, signal integrity analysis