Jasper, Perl, Python, Asic verification, verification methodologies, Synopsys Magellan, Uvm, systemverilog, Cadence IEV, VC Formal, functional coverage, SVA

Pcie, CHI, Ace, UVM methodology, UCIe, systemverilog, Axi, AMBA, RAS features, CXL, debugging skills, SVA

static timing analysis, Digital Logic Design, Perl, Verilog, Python, Scripting, Tcl, Synthesis, memory subsystems, cdc, SOC design, Uvm, IP integration, systemverilog, Rtl Design, Axi, formal verification, EDA tool flows, LINT, Verification, bus architectures, automation of design flows

Tcp, Pcie, Ethernet, System Verilog, RDMA, Data path verification performance tests, Building test benches from scratch, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

C, coverage closure, microprocessor ISA, coverage planning, Data-Consistency verification, power management verification, testbench development, low power verification flows, clocking reset power-up sequences, systemverilog

CPU GPU benchmark characterization, SOC design verification, mobile SOC performance model development, Linux drivers, runtime, workload characterization, performance analysis tools, systemverilog, Performance Analysis

Shell, Perl, Verilog, Python, Tcl, UVM methodology, Cadence, systemverilog, Functional and code coverage, Simulation and debugging concepts, Verification tools from Synopsys, Siemens EDA

Usb, Ovm, Soc, DDR, Pcie, Ethernet, System Verilog, Ip, Uvm, Video, MIPI, VMM, ARM Based SoC Verification, HDMI, dsi, CSI