power optimization , Perl, Scripting, Python, Tcl, Cadence, Mentor, Timing Analysis, Physical Design, Signal Integrity, EDA Tools, Synopsys

redhawk , Perl, Tcl, Dc, Deep sub-micron designs, Pt, Logic equivalence checking, Formality, VSLP, LVS, ICC, STA timing, Physical Design, Calibre, Timing Closure, Synthesis, SOC design, DRC, Place And Route, Low Power checking

PERL, Python, Tcl, Sta, CTS, Timing Convergence, ICC2, RTL2GDSII flow, Ir, Tempus, Block-level and Full-chip Floor-planning, primetime, Innovus, Synthesis, Physical Verification, Layout Closure, Physical Design, High Frequency Design Methodologies, Seahawk, Place And Route, ECO Timing Closure

Scripting, Physical Verification, Physical Design, PG creation, ESD latch-up, RDL knowledge, Innovus, floorplanning

Static Timing analysis, Perl, Tcl, Clock Planning, SoC designs, Power Plan, Digital place and route, Floor Planning, Clock Tree Synthesis, Parasitic Extraction, PnR Signoff

Docker, Python, AI ML background, Optimization, SOC domain, graph algorithms, combinatorial algorithms, geometry packages such as shapely

Fusion Compiler, IC Compiler, Cadence Genus, Block-level PnR, Physical Design, Innovus