4-14 years
800000 - 5000000 INR
2 months ago 261 Applied
Job Description

At-least 4 years of experience in System Verilog HVL.
At-least 3 year of experience in OVM/UVM/VMM/Test Harness.
Hands on experience of developing assertion, checkers, coverage and scenario creation.
Must have executed at-least 1 SoC Verification project
Experience in developing test and coverage plan, Verification environment and validation plan.
Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required.

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