Technical Manager STA & Synthesis

Technical Manager – STA & Synthesis

Location: Bengaluru, India

Experience: 13–18 Years

Role Summary

We are looking for a highly technical STA & Synthesis Technical Manager to lead timing and synthesis closure for high-performance SoCs on advanced process nodes. This is a hands-on technical leadership role requiring deep expertise in RTL-to-GDS implementation, timing convergence, methodology development, and cross-functional collaboration to deliver first-pass silicon.

Key Responsibilities

• Lead RTL synthesis and Static Timing Analysis (STA) for complex ASIC/SoC designs from RTL through tapeout.
• Drive timing closure across all PVT corners, including setup, hold, SI, OCV/AOCV/POCV, MCMM, and variation-aware optimization.
• Own synthesis optimization for Power, Performance, and Area (PPA) using advanced synthesis methodologies.
• Develop and validate SDC constraints, timing budgets, clock architecture, and timing signoff strategies.
• Drive ECO implementation, timing correlation, and convergence across RTL, synthesis, place & route, and signoff.
• Partner with RTL, Physical Design, DFT, Architecture, CAD, and Design Verification teams to resolve complex timing and implementation challenges.
• Develop scalable STA and synthesis methodologies, automation frameworks, and flow improvements.
• Mentor senior engineers while providing technical leadership across multiple SoC programs.

Required Skills

• 13–18 years of hands-on experience in ASIC/SoC STA and Synthesis.
• Deep expertise in RTL Synthesis, MCMM Timing Closure, Setup/Hold Analysis, SI, Crosstalk, OCV/AOCV/POCV, CRPR, CDC, and Timing ECOs.
• Strong understanding of clock tree architecture, timing constraints (SDC), low-power implementation (UPF/CPF), and PPA optimization.
• Hands-on experience with Synopsys Design Compiler/NXT, Fusion Compiler, PrimeTime (PX/SI), Cadence Genus, Tempus, and equivalent signoff tools.
• Experience with advanced technology nodes (7nm, 5nm, 3nm, and below).
• Strong scripting skills using Tcl, Python, Perl, or Shell for automation and methodology development.
• Proven experience delivering multiple high-performance SoCs from synthesis through timing signoff.

Preferred Qualifications

• Experience with CPU, GPU, AI/ML, Networking, Datacenter, Mobile, or Automotive SoCs.
• Strong understanding of Physical Design interactions, DFT impacts, and full-chip timing closure.
• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related discipline.
• Demonstrated technical leadership, mentoring, and ability to drive execution across globally distributed engineering teams.