Drive physical design implementation which includes package co-design, floor planning, power grid design and signoff, place and route, timing closure, physical verification checks.
Job Description
In your new role you will:
- Responsible for leading Physical Design and Timing Closure of low power SoCs.
- Responsible to achieve die area, performance, power goals for hierarchical blocks and top.
- Drive physical design implementation which includes package co-design, floor planning, power grid design and signoff, place and route, timing closure, physical verification checks.
- Influence tools, flows and methodology activities to improve upon QoR.
- Interact with cross-functional team members to improve design, methodology and process aspects.
- Enable next generation of place and route engineers via mentoring and thought leadership.
Your Profile
You are best equipped for this task if you have:
- Hands-on experience in physical design implementation and timing closure of large blocks/top
- Expert user of industry standard tools for physical design and signoff.
- Expert in scripting languages (shell, perl, tcl) and Make flow
- In-depth knowledge of 28nm/16nm/12nm technologies and associated physical design challenges
- Deep understanding of low power design techniques and implementation methodologies
- Should be self-motivated and take initiatives to drive new methodologies
- Should have strong written and verbal communication skills
Contact:
[Confidential Information]
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