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Senior Staff Engineer -Analog Mixed Signal Design Verification

Vitestork Consulting Private Limited

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8-15 Years
4 months ago
95 Viewed
219 Applied

Job Description

Senior Staff Engineer (Mixed Signal Design Verification)

Tasks and Responsibilities:

Modeling of analog blocks like Bandgap, LDO, ADC for top level SV/UVM verification
Implement and validate analog behavioral models for chip level DMS simulations.
Top level mixed signal test planning, test creation/debug, regression
Create, debug, and run test-benches and regressions for verification sign-off.
Interact with analog and digital design engineers for feature extraction.
Verification flow setup using Cadence AMS ADE and command line (xrun and runams)
Develop support utilities for verification automation, test bench automation, regression, and
other verification enhancements to improve productivity and functional coverage.

Required education and experience

M.Tech/B.Tech in Electronics with 8-12 years experience on Analog Mixed-Signal Verification.
Good understanding of analog and mixed-signal Verification flows and methodologies
VerilogAMS and systemverilog real number modelling experience
Familiarity with System Verilog and UVM, including writing checkers and assertions etc.
Working knowledge of scripting languages (Shell, Python etc)
Understanding on design sync and data base management system such as SVN
Basic understanding of I2C and SPI desired but not essential
Required personal skills
Excellent presentation and communication skills
Initiative, enthusiasm, systematic and analytic approach
Team player/driver and a self-starter with ability to work independently.
Fluency in English written and verbal
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Semiconductors R & D company.

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FUNCTIONS
IT/ Software Development - Other
INDUSTRY
Recruitment/ Staffing/ RPO
SKILLS/ROLES I HIRE FOR
Networking, Semiconductor, Testing, ..
LEVEL HIRING FOR
Junior Level, Mid Level, High Level, Top Management
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