Senior Lead Analog Design Engineer: High Speed Interfaces

NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, we are driving innovation in the secure connected vehicle, end-to-end security & privacy and smart connected solutions markets.

NXP's Precision Analog & Interfaces product line is developing products which bridge high and low speed wired interfaces with millimeter wave wireless technologies and provide ground-breaking and innovative solutions to the consumer, computing, and industrial markets

Responsibilities Include

• Evaluate circuit architectures and concepts.
• Detailed transistor level design of analog circuits and supporting biasing and power
• Provide innovative technical solutions to address design challenges leading to continuous improvement of various design blocks and sub-systems
• Work with the system and digital team in Micro Arch Evaluation, defining interfaces and calibration schemes
• End to end ownership of design execution, performance and reliability verification
• Guide junior designers for sub-blocks and layout designer for an optimized layout
• Documentation of design and presenting reviews to peers and internal approvers.

Candidate Profile

• Master's/Bachelor's Degree in Electrical/Electronic engineering from a reputed, university with an emphasis in VLSI/IC design.
• 5+ years of extensive experience in design and development of analog/mixed-signal IPs in advanced CMOS technologies
• Extensive experience with at least one of the following blocks: CDR, Tx Driver, RX CTLE, L-based Matching network, DFE, VGA, PLL
• Proficient with using analog circuit design EDA tools such as Cadence ADE. Have knowledge of basic transistor models (CMOS).
• Strong in Analog building blocks design and their tradeoff for power, area and jitter optimization. Good understanding matching, s-parameter, equalization, ISI, noise/jitter modelling and simulations is desirable.
• Strong skills in bandwidth enhancement, thermal noise suppression and linearity improvement techniques is a big plus.
• Experience in designing high speed SerDes PHY Tx, Rx and/or Clocking sub-systems in multi Gbps range for USB3.x, USB4, DP or Thunderbolt.
• Excellent verbal and written communication skill is desired. A creative and innovative mindset and ready to understand new concepts, result driven and a good team player.
• Having technical publications and/or patents is a plus.