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Senior Design Verification Engineer

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Job Description

Our client is working on next-generation Semiconductor programs for its global clientele and looking for top talent in VLSI technologies with the following skillsets:

They are looking for Senior Design Verification Engineer to be based at Bangalore with the following:

4+years to experience in UVM based ASIC verification
ASIC DV experience with UVM methodologies
Experience in developing UVM-based SV test-benches.
Experienced with defining block, sub-system or SOC top level test plans.
Hands-on experience with verification environments, architecture definitions and development.
Strong PCIe and NVMe experience.
Relevant experience with one or more of UFS/MIPI, DDR and CPU sub-systems.
Understanding and knowledge of verification methodologies, flows and quality metrics.
Experience with Functional Coverage, Constrained Random, Reusable verification environments
Individual with 4 to 20 years of experience with 4+ years in Design Verification will be preferred.

Kindly send your profile to tulsiarora(at)

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Last Updated: 14-05-2024 00:25:29 PM
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