Job Description
The role will be built around the experience you have, but here s some requirements that we feel may be beneficial for you to have:
- Low Power Verification Expertise: Leverage your strong experience with UPF (Unified Power Format) to ensure our designs are power- efficient.
- Tape -Out Success: You ve been part of multiple tape-outs, mastering PG netlist regression closure.
- Debug Ninja: Your SDF (Standard Delay Format) timing simulation skills are top-notch, allowing you to pinpoint and resolve failures.
- UVM Champion: Dive deep into UVM (Universal Verification Methodology) to create robust verification plans
- . End-to-End SOC Experience: From concept to tape-out to bring-up, you ve seen it all.
- Embedded Systems Know-How: Taping out large SOC systems with ARM cores Check.
- Bus Architecture Wizard: AXI, APB, AHB - you ve verified them all in a UVM environment.
- Coverage-Driven Verification: Craft UVM-based coverage plans from design specs, ensuring thorough testing
- Low Power Design Guru: Dive into UPF integration, boot sequences, and HW/SW interactions.
- ARM Insights: Understand ARM s low-power design principles and power policy units.
- SOC Architectural Savvy: From PLLs to secured boot schemes, you know the SOC landscape.
- Protocol Proficiency: SPI, I2C, UART - you re fluent. Plus, high-speed protocols like SDIO and USB2.0
- . Scripting Sorcerer: Python and Perl are your trusty sidekicks.
- Team Player Extraordinaire: Collaborate, communicate, and solve challenges together.
- Qualifications : B.Tech /B.E/M.Tech in EE/ECE with 5+ years of hands-on DV experience using System Verilog.
