Define and implement verification concepts for complex IPs/SoC using state-of-the-art methodologies such as metric driven, formal and emulation-based verification as well as HW/SW co-verification
Job Description
In your new role you will:
- Define and implement verification concepts for complex IPs/SoC using state-of-the-art methodologies such as metric driven, formal and emulation-based verification as well as HW/SW co-verification
- Develop the architecture of advanced testbenches using SV/UVM
- Coordinate the overall verification strategy
- Define and control verification management activities such as Verification planning, Verification tracking and reporting
- Control and review work process compliance ensuring high-quality Verification sign-off
- Define and implement Power aware simulation and Gate level simulations as per the requirements
Your Profile
You are best equipped for this task if you have:
- Education: B.E./B.Tech/M.E./M.Tech
- Experience: MS with 12+ years / BS with 14+ years
- Candidate should have strong expertise in digital verification using System Verilog and UVM. Should have the expertise in developing verification infrastructure for complex IPs and SoCs using the state other art methods.
- Having knowledge in ARM based SoC verification covering RTL, Power Aware and Gate level simulations is preferable.
- Exposure to deployment of automation methods and formal verification methodologists preferable.
- Knowledge on Ethernet (IEEE 802.3), MIPI protocols, Display Port is highly preferable.
Contact:
[Confidential Information]
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