Principal Engineer - Verification / AMS / SerDes

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Central Engineering AMS‑IP delivers high‑quality analog and mixed‑signal IP and verification for Marvell's advanced IPs, SoCs and platforms. The team provides scalable, reusable solutions across high‑speed interfaces (SerDes, DDR, D2D, PCIe, Ethernet PHY components) and advanced process nodes (5nm, 3nm, 2nm), enabling first‑time‑right silicon, reduced integration risk, and faster time‑to‑market through strong design‑verification convergence and system‑level validation.

What You Can Expect

Role Summary

The Principal Engineer will providetechnical and methodological leadershipacross complexhigh‑speed SerDes, AMS, and Central Engineering verification programs. This role requires deep hands‑on expertise combined with the ability todefine verification strategy, influence architecture, mentor senior engineers, and drive execution excellence across multiple projects and nodes.

Key Responsibilities

.Ownend‑to‑end verification strategy and executionfor complexSerDes / AMS / mixed‑signal IPsacross multiple process nodes (e.g., 5nm, 3nm, 2nm).

.Define and driveverification architecturespanning digital, AMS, firmware‑assisted, and system‑level verification.

.Leaddesign‑verification convergence, influencing architecture, register definition, calibration flows, and feature feasibility.

.Drive resolution ofcomplex cross‑domain issuesinvolving RTL, AMS, firmware, VIPs, and silicon behaviors.

.Serve as thetechnical authority and escalation pointfor hard verification, coverage, debug, and sign‑off challenges.

.LeadGate‑Level Simulation (GLS)strategy, power‑aware verification, CDC/RDC validation, and post‑silicon correlation.

.Define verification approaches fornew features.

.Mentor juniors, raising the bar ontechnical rigor, ownership, and execution discipline.

.Drivemethodology, tooling, and productivity improvements, including automation and AI‑assisted verification where applicable.

.Proactively identifytechnical and schedule risksand drive early mitigation across teams.

What We're Looking For

Required Technical Qualifications

.14+ years of strong hands‑on experience inverification of IP / AMS systems.

.Deep expertise in one or more areas:

. High‑speed SerDes(PCIe, Ethernet, D2D, PAM4/PAM2)

. AMS / Mixed‑Signal verification

. Register modeling, firmware‑driven flows

.Strong proficiency inSystemVerilog, UVM, and advanced verification methodologies.

.Experience withprotocol/VIP integration(Synopsys, Cadence, Mentor, Avery, etc.).

.Hands‑on experience withGLS, power‑aware verification, timing‑aware flows, and silicon bring‑up support.

.Ability to analyze and debug issues spanningpre‑silicon to post‑silicon correlation.

.Strong understanding ofsystem‑level behavior, not just block‑level verification.

Leadership & Behavioral Expectations

.Acts as atechnical multiplier, enabling success across multiple teams and projects.

.Leads throughinfluence, credibility, and ownership, not hierarchy.

.Makessound trade‑offs under ambiguity, balancing quality, schedule, and risk.

.Communicates complex technical issues withclarity and structureto diverse audiences.

.Modelsengineering excellence, integrity, and accountability.

.Invests indeveloping others, scaling impact beyond personal execution.

Nice‑to‑Have / Differentiators

.Experience definingverification frameworks reused across IPs / programs.

.Innovation inAI‑assisted verification, automation, or coverage optimization.

.Publications, patents, or conference presentations (DVCon, VLSI‑D, internal forums).

.Experience working acrossglobally distributed teamsand central engineering models.

Success Criteria

.Raises thetechnical bar and predictabilityof SerDes/AMS verification.

.Enables teams to execute fasterwithout compromising quality.

.Becomes atrusted technical voicefor architecture, verification strategy, and leadership.

.Leaves behind scalable frameworks, stronger engineers, and durable methodologies.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

#LI-RV1