Job Details
Job Description:
- Directs and manages a team of physical design engineers responsible for the physical design implementation of a chip design, subsystem, or block including clocking, timing, and integration.
- Provides guidance on physical design implementation and analyzes layout designs, power delivery, place, route, clock tree synthesis, and other aspects of physical design.
- Manages development of complex layout integrated circuit designs, simulation designs, RTL to GDS, logic synthesis, and oversees documentation for SoC development.
- Reviews circuit layouts architectures and prototypes, ensures issue resolution, and optimizes circuit output.
- Oversees physical design verification flow at block and chip level and makes recommendations to fix violations for current and future product architecture.
- Ensures schedule and landing zone requirements of the block, subsystem, or SoC are met. Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results.
- Drives results by inspiring people, role modelling Altera values, developing the capabilities of others, and ensuring a productive work environment.
- This Position is for future Hyderabad site.
Qualifications
- B.Tech/M.Tech/M.S. in Electrical Engineering, Electronics, or related field.
- Ph.D. preferred but not mandatory.
- 15+ years of experience in Physical Design.
Job Type
Regular
Shift
Shift 1 (India)
Primary Location:
New Delhi, India (Remote)
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
