MSEE/BSEE with 8+ years in chip design verification.
Experience in planning the verification process and creating realistic schedule estimates.
Experience in High Level Verification languages: System Verilog is a must.
Strong experience in high level Object Oriented test bench environments such as UVM or any equivalent.
Experience in verifying complex verification blocks like PLL calibrations, multi clock, reset domain designs and mixed signal interfaces is a big plus.
Knowledge of Ethernet and OTN standards and IEEE 802.3 Physical layer clauses like Cl.72, 93, 91 etc. is preferred
Excellent knowledge of PCIE protocol - Gen3 and above is a plus
Deeper understanding of PLLs/CDR concepts/AMS interfaces and networking IP designs are preferred.
Experience in developing coverage-driven verification test plans
Experience writing test specifications (plans) and creating directed and random test cases.
Experience in developing constrained random verification environment
Experience managing regression analysis
Experience in reviewing and critiquing of test bench and test plans
Strong debugging skills of Verilog RTL & test environment is desired
Able to adopt the use of new techniques and methodologies and promote their use within the project.
A high level of pro-activity, self-organized and problem solving.
Experience with assertion based verification is preferred
Verification experience in SERDES, Ethernet Networking in Verilog is a big plus.
Experience with scripting languages such as PERL, TCL Unix Scripting is highly desirable
