Dft Engineer

Job Description

Should have worked hands-on extensively on full chip DFT design,

implementation, vector generation/verification, JTAG, boundary scan and simulation.

Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus.

Should have participated in successful tapeouts ofSoC/ASIC chips at 14nm or below and achieved test targets.

Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA.

Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process

Excellent problem solving and debugging skills. Proactive in nature

Leading junior teams, Mentoring/Training and Project leadership.

Excellent Customer interaction, Communication and Team work skills

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