Perforce, Git, Jtag, Perl, Verilog, System Verilog, Python, Tcl, Mentor Questa, Cadence Xcelium, Formal Property Verification tools, clock gating, Uvm, UPF, Synopsys VCS, APB, CRI, low-power design techniques, IJTAG

Python, Tcl, Analog mixed-signal IC design, Verilog-AMS, AMS Designer, behavioral modeling, Cadence Virtuoso, Verification, systemverilog, Spectre