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ðŸ¹ THE ROLE

As a PHY‑V Lead, you will own physical verification sign-off, full-chip integration, and packaging interface (RDL) planning for advanced SoC programs. You will drive DRC/LVS clean tapeouts, integration quality, and sign-off predictability across complex multi-IP designs.

This role requires strong expertise in physical verification, top-level integration, and advanced packaging alignment, along with the ability to lead cross-functional execution across PD, Analog, and Packaging teams.

ðŸ¹ THE PERSON

Strong technical leader with deep PD + Physical Verification understanding
Proven ownership of sign-off closure for complex SoCs
Ability to drive execution across multiple teams and dependencies
Detail-oriented with focus on quality, manufacturability, and schedule predictability
Comfortable operating in high-pressure tapeout environments

ðŸ¹ KEY RESPONSIBILITIES

âœ… Physical Verification & Sign-off Ownership

Drive end-to-end DRC, LVS, ERC, antenna closure at block and full-chip level
Define and enforce sign-off methodology and quality criteria
Own foundry rule decks, waivers, and risk assessments
Deliver sign-off clean GDS for tapeout

âœ… SoC / Full-Chip Integration

Lead top-level integration of IPs/macros into SoC
Own:

GDS assembly
Hierarchical LVS reconciliation

Resolve:

Boundary issues
Connectivity mismatches
Integration conflicts

Ensure robust integration across internal and third-party IPs

âœ… RDL & Packaging Integration

Drive RDL planning and bump mapping strategy
Define IO escape routing and die-package interface
Collaborate with Packaging, SI/PI, and system teams
Enable flip-chip / 2.5D / 3D integration readiness

âœ… Tapeout Execution & Tracking

Own sign-off checklist, closure tracking, and tapeout readiness
Lead tapeout reviews and milestone tracking
Drive cross-team closure to meet schedule and quality targets

âœ… Methodology & Flow Development

Define and improve physical verification flows (Calibre/ICV/Pegasus)
Drive:

Automation (TCL/Python)
Runtime optimization
Debug efficiency

Establish best practices for hierarchical and incremental sign-off

âœ… Debug & Issue Resolution

Lead debug of:

Complex DRC violations
LVS mismatches (shorts/opens/connectivity issues)

Drive closure with PD/layout teams
Minimize waivers and ensure risk-managed sign-off

âœ… Leadership & Collaboration

Lead and mentor PHY‑V engineers
Act as primary escalation point for sign-off issues
Interface with:

PD / PnR teams
Analog/layout teams
Packaging and foundry teams

ðŸ¹ REQUIRED QUALIFICATIONS

B.Tech / M.Tech in Electronics / Electrical Engineering
10-15+ years in Physical Design / Physical Verification / SoC Integration
Strong expertise in:

DRC, LVS, ERC, antenna checks
Tools: Calibre / ICV / Pegasus

Solid understanding of:

Full PD flow (RTL GDS sign-off)
Advanced process nodes (7nm and below)

ðŸ¹ PREFERRED QUALIFICATIONS

Experience in:

Full-chip SoC integration and GDS assembly
RDL planning and advanced packaging flows

Exposure to:

IR/EM, SI/PI, PEX, reliability checks
Chiplet / 2.5D / 3D-IC methodologies

Strong scripting (TCL/Python) for automation

#LI-BM2

Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available

This posting is for an existing vacancy.

Phy- V Lead