Perl, Verilog, Python, Makefiles, RTL Build flows, SOC Assembly, pinmuxing, SoC Verification, Design Automation, chip level front-end design, Physical Design, Rtl Design, Dft, Synthesis, padring, retiming, System-On-Chip design implementation flow, SOC integration

Perforce, static timing analysis, Shell, Verilog, Version Control Systems, Scripting Languages, Python, Git, Perl, Tcl, cdc, Simulation, formal verification, EDA Tools, Rtl Design, Synthesis, SoC Architecture Design, LEC, AMBA protocols, systemverilog, Axi, APB, LINT, AHB, SoC Integration

Usb, Jtag, Pcie, Perl, Ethernet, Python, System Verilog, UVM methodology, Design for Debug, scripting in Linux Unix environments, SoC architecture verification, TSN, ARM based SoC verification, High speed USB