code coverage , C, Shell, Perl, Verilog, Debugging, Flash, Python, System Verilog, Tcl, interconnect, Memory, UVM methodology, Microprocessor architecture, Metric Driven Verification, Rom, formal verification methodologies, Axi, MRAM, AHB, SoC Verification, Ram, constrained random methodologies

arm architecture , Usb, C, DDR, Pcie, Perl, Ethernet, Systemc, Tcl, SoC DV execution, Uvm, assertion-based formal verification tools, HBM

Verilog, systemverilog, Digital and analog simulation tools, Uvm, PrimeSim, Verification strategy, Design Verification, Hspice, FineSim

arm architecture , C, Ethernet, Pcie, Usb, DDR, assertion-based formal verification tools, Uvm, SoC DV execution, HBM, hardware emulation support