Jtag, Perl, Verilog, Python, Tcl, Sta, MBIST, Siemens Tessent, Synopsys TestMAX, systemverilog, DFT Compiler, Scan Insertion, Physical Design, Cadence Modus, RTL synthesis, ATPG, Scan Compression, DFT Architecture

automatic test pattern generation , DFT Scan Compression, Design for Test, ATPG Silicon Validation