Perl, Verilog, Python, Makefiles, fuse floorsweep design, RTL Build flows, SOC Assembly, Design Automation, Rtl Design, padring, System-On-Chip design implementation flow, SOC integration

C, Scripting Languages, Gdb, Verilog, Python, Indago, Micro-Architecture, ASIC Architecture, SOC design, Cadence, Verification, Physical Design, Timing Closure, Rtl Design

Perforce, static timing analysis, Shell, Verilog, Version Control Systems, Scripting Languages, Python, Git, Perl, Tcl, cdc, Simulation, formal verification, EDA Tools, Rtl Design, Synthesis, SoC Architecture Design, LEC, AMBA protocols, systemverilog, Axi, APB, LINT, AHB, SoC Integration

Usb, Jtag, Pcie, Perl, Ethernet, Python, System Verilog, UVM methodology, Design for Debug, scripting in Linux Unix environments, SoC architecture verification, TSN, ARM based SoC verification, High speed USB