C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, TLM

Perl, Shell scripting, DFT verification, VCS simulation tool, Synopsys Tetramax DFTMAX, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Mentor testkompress, Design for Test methodologies

Perl, Shell scripting, DFT verification, VCS simulation tool, IEEE1500, Synopsys Tetramax, Scan memory BIST, Verilog RTL design, JTAG 1149.x, Design for Test methodologies, Mentor testkompress

Shell, Jtag, Python, Tcl, scan compression, IEEE 1149.x, MBIST, DFT implementation methodology, DFT EDA tools, IEEE 1687, ATPG, hierarchical DFT methodologies, LBIST, automation and scripting skills

Tcl Scripting, Perl, Dft, Gate level simulations, Zero delay Timing Delay simulations, PD flow knowledge, ATPG Pattern generation, Timing Formal verification, JTAG P1500 protocols, SCAN DRC