routing, Perl, Python, Tcl, ASIC design flow, Synthesis, Timing Analysis, signoff, EDA Tools, Timing Closure, Placement, PPA optimization, AI-driven productivity tools, RTL-to-GDSII

Automation, Shell Scripting, Debugging, Python, Chip Design, Mixed-Signal Design, Customer Engagement, IP Characterization

client server technologies , C, Phyton, Machine Learning, Big Data, Tcl, Perl, formal methods, Uvm, vManager, EDA Tools, systemverilog, database architectures, VHDL, verification solutions, Functional Verification flows